This invention relates to processing of semiconductor wafers and, more particularly, to integrated processing systems and methods for doping a workpiece with impurity materials over a range of energies, including very low energies.
Ion implantation has become a standard technique for introducing conductivity-altering impurities into semiconductor wafers. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded into the crystalline lattice of the semiconductor material to form a region of desired conductivity.
Ion implantation systems usually include an ion source for converting a gas or a solid material into a well-defined ion beam. The ion beam is mass analyzed to eliminate undesired species, is accelerated to a desired energy and is directed onto a target plane. The beam may be distributed over the target area by beam scanning, by target movement or by a combination of beam scanning and target movement. Examples of prior art ion implanters are disclosed in U.S. Pat. No. 4,276,477 issued Jun. 30, 1981 to Enge; U.S. Pat. No. 4,283,631 issued Aug. 11, 1981 to Turner; U.S. Pat. No. 4,899,059 issued Feb. 6, 1990 to Freytsis et al.; U.S. Pat. No. 4,922,106 issued May 1, 1990 to Berrian et al.; and U.S. Pat. No. 5,350,926 issued Sep. 27, 1994 to White et al.
A well-known trend in the semiconductor industry is toward smaller, higher speed devices. In particular, both the lateral dimensions and the depths of features in semiconductor devices are decreasing. State of the art semiconductor devices require junction depths less than 1,000 Angstroms and may eventually require junction depths on the order of 200 Angstroms or less.
The implanted depth of the dopant material is determined, at least in part, by the energy of the ions implanted into the semiconductor wafer. Shallow junctions are obtained with low implant energies. However, ion implanters are typically designed for efficient operation at relatively high implant energies, for example in the range of 20 keV to 400 keV, and may not function efficiently at the energies required for a shallow junction implantation. At low implant energies, such as energies of 2 keV and lower, the current delivered to the wafer is much lower than desired and in some cases may be near zero. As a result, extremely long implant times are required to achieve a specified dose, and throughput is adversely affected. Such reduction in throughput increases fabrication cost and is unacceptable to semiconductor device manufacturers.
Plasma doping systems have been studied for forming shallow junctions in semiconductor wafers. In one type of plasma doping system, a semiconductor wafer is placed on a conductive platen, which functions as a cathode, located in a plasma doping chamber. An ionizable gas containing the desired dopant material is introduced into the chamber, and a voltage pulse is applied between the platen and an anode, causing formation of a glow discharge plasma having a plasma sheath in the vicinity of the wafer. The applied voltage pulse causes ions in the plasma to cross the plasma sheath and to be implanted into the wafer. The depth of implantation is related to the voltage applied between the wafer and the anode. Very low implant energies can be achieved. Plasma doping systems are described, for example, in U.S. Pat. No. 5,354,381 issued Oct. 11, 1994 to Sheng; U.S. Pat. No. 6,020,592 issued Feb. 1, 2000 to Liebert et al.; and U.S. Pat. No. 6,182,604 issued Feb. 6, 2001 to Goeckner et al.
In other types of plasma systems, known as plasma immersion systems, a continuous RF voltage is applied between the platen and the anode, thus producing a continuous plasma. At intervals, a high voltage pulse is applied between the platen and the anode, causing positive ions in the plasma to be accelerated toward the wafer.
The fabrication of state of the art semiconductor devices may require a number of implant steps at energies ranging from very low to relatively high. The low energy processing steps may require long implant times in a beamline ion implanter or the expense of a plasma doping system in addition to the beamline ion implanter. Accordingly, there is a need for improved processing systems and methods for implanting dopant materials into workpieces over a range of energies, including very low energies.
According to a first aspect of the invention, apparatus is provided for processing a semiconductor wafer. The apparatus comprises a process chamber, a beamline ion implant module for generating an ion beam and directing the ion beam into the process chamber, a plasma doping module including a plasma doping chamber that is accessible from the process chamber, and a wafer positioner for positioning a semiconductor wafer in the path of the ion beam in a beamline implant mode and for positioning the semiconductor wafer in the plasma doping chamber in a plasma doping mode.
The plasma doping chamber may be located within the process chamber and may be movable between a plasma doping position and a retracted position. A first vacuum pump may be coupled through a first pumping port to the process chamber, and a second vacuum pump may be coupled through a second pumping port to the plasma doping chamber. The plasma doping chamber may be isolated from the process chamber in the plasma doping mode.
The wafer positioner may comprise a platen for holding the wafer and a platen positioner for positioning the platen. The platen may be movable between a beamline implant position, a plasma doping position and a wafer transfer position. The plasma doping chamber may include an opening in communication with the process chamber, wherein the platen is movable into sealed engagement with the opening in the plasma doping chamber. The platen may comprise an electrostatic wafer clamp. The platen positioner may comprise means for mechanically scanning the platen with respect to the ion beam in the beamline implant mode.
The apparatus may further comprise a controller for selecting the beamline implant mode or the plasma doping mode and for controlling the wafer positioner according to the selected mode. The apparatus may further comprise a wafer handler for loading a wafer on the platen for processing and for removing the wafer from the platen following processing.
The plasma doping module may include an anode positioned within the plasma doping chamber and a pulse source coupled between the anode and the platen. In one embodiment, the platen is connected to a reference potential and pulses are applied to the anode by the pulse source. In another embodiment, the anode is connected to a reference potential and pulses are applied to the platen by the pulse source.
The plasma doping module may further include a hollow electrode surrounding a space between the anode and the platen. In one embodiment, a hollow electrode pulse source is coupled to the hollow electrode. In another embodiment, the hollow electrode is electrically coupled to the anode.
The apparatus may further comprise an anode positioner for controlling the spacing between the anode and the platen. A chamber positioner may be provided for moving the plasma doping chamber between a plasma doping position and a retracted position.
In one embodiment, a vacuum pump is coupled to the process chamber. The plasma doping module includes a controlled conductance aperture between the interior volume of the plasma doping chamber and the process chamber, and a process gas source coupled to the plasma doping chamber. The interior volume of the plasma doping chamber is pumped by the vacuum pump through the controlled conductance aperture in the plasma doping mode. In another embodiment, a process gas source and a vacuum pump are coupled to the plasma doping chamber. The interior volume of the plasma doping chamber is pumped by the vacuum pump in the plasma doping mode.
According to another aspect of the invention, a method is provided for processing a semiconductor wafer. The method comprises the steps of positioning a semiconductor wafer in a process chamber, processing the wafer in the process chamber by ion implantation in a beamline implant mode, and processing the wafer in the process chamber by plasma doping in a plasma doping mode.
The step of processing the wafer by ion implantation may comprise directing an ion beam at a surface of the wafer. The step of processing the wafer by plasma doping may comprise processing the wafer in a plasma doping chamber that is accessible from the process chamber. The step of positioning the wafer may comprise mounting the wafer on a support platen located in the process chamber. The method may further comprise the step of moving the plasma doping chamber between a plasma doping position and a retracted position.